Clock jitter analyzed in the time domain
August 9, 2011 by Design With TI+
Filed under Signal Chain
Part 1 of this three-part article series focused on how to accurately estimate jitter from a clock source and combine it with the aperture jitter of an ADC. In this article, Part 2, that combined jitter will be used to calculate the ADC’s signal-to-noise ratio (SNR), which will then be compared against actual measurements.
Clock Solution for High-Speed ADCs
August 9, 2011 by Design With TI+
Filed under Interface, Signal Chain
This application report highlights the limiting agents associated with the clock source that adversely affect the ADC signal-to-noise performance. The performance of the ADS5527 ADC clocked with the CDCE62005 is shown and compared to ideal baseline performance. Additional improvement topologies are presented, along with measured results that show the CDCE62005 can meet or exceed the specifications at high sampling rates, and even at the more demanding high input frequencies.
Ethernet Clock Generation
August 9, 2011 by Design With TI+
Filed under Interface, Signal Chain
This application report is a guide for using Texas Instruments CDCM6100x in an Ethernet LAN and WAN application as a clock distributor and clock synthesizer along with measured jitter performance results.
